Converter for converting an input voltage to an output voltage

ABSTRACT

A converter for converting an input voltage (U i ) between a first supply terminal ( 1 ) and a second supply terminal ( 2 ) to an output voltage (U 0 ), which converter includes switching means (S 0 ) which, in the operating state of the converter, are alternately switched on and off under the control of a control signal (V cntrl ), an inductive element (T) which, in conjunction with the switching means (S 0 ), forms a series circuit which is coupled between the first supply terminal ( 1 ) and the second supply terminal ( 2 ), a control circuit (CNTRL) for supplying the control signal (V cntrl ), and evaluation means (EVMNS) for evaluating a voltage (U S ) across the switching means (S 0 ), which voltage (U S ) exhibits ringing, and for supplying the control circuit (CNTRL) with information causing the switching on of the switching means (S 0 ) during a given valley of the voltage (U S ) across the switching means (S 0 ). The converter remains locked to said valley for as long as the frequency of the control signal (V cntrl ) is within a given frequency window. The converter also includes a frequency control circuit (FC) for controlling the frequency of the control signal (V cntrl ) within the frequency window. If the frequency reaches the lowest frequency or the highest frequency of the frequency window, the information is adapted in such a way that the converter is locked to another valley of the voltage (U S ) across the switching means (S 0 ), so that the frequency of the control signal (V cntrl ) remains within the frequency window.

[0001] The invention relates to a converter for converting an inputvoltage between a first supply terminal and a second supply terminal toan output voltage, which converter includes switching means which, inthe operating state, are alternately switched on and off under thecontrol of a switching control signal, an inductive element which formsa series circuit in conjunction with the switching means, which seriescircuit is coupled between the first supply terminal and the secondsupply terminal, a control circuit for supplying the switching controlsignal, and evaluation means for evaluating a voltage across theswitching means, said voltage exhibiting oscillating, and for supplyingthe control circuit with information so as to ensure that, generallyspeaking, the switching means is switched on only during a given localvalley of the voltage across the switching means.

[0002] A converter of this kind is shown in FIG. 1 and is known fromU.S. Pat. No. 5,754,414. A primary winding of a transformer 12 iscoupled, together with a switching transistor 18, between a first supplyterminal V_(S) and a second supply terminal GND in order to receive aninput voltage V_(S). The transformer 12 is also provided with asecondary winding 30. A voltage delivered by the secondary winding 30 isrectified by means of a diode 32 and subsequently smoothed by asmoothing capacitor 34, so that an output voltage V₀ is deliveredbetween an output terminal V₀ and the second supply terminal GND. Theoperation of the known converter will be described in detail hereinafterwith reference to the FIGS. 1 to 3. Between the instants t₀ and t₁ thebase voltage V_(b) (relative to the second supply terminal GND) of theswitching transistor 18 is substantially equal to 0 volts, so that theswitching transistor 18 is not turned on. Consequently, the collectorvoltage V_(c) (relative to the second supply terminal GND) of theswitching transistor 18 is substantially equal to the input voltageV_(S). At the instant t₁ the base voltage V_(b) is increased to such anextent that the switching transistor 18 is fully turned on, so that thecollector voltage V_(c) becomes practically equal to 0 volts. Thevoltage V_(b) remains high until the instant t₂. As a direct consequencethe voltage across the primary winding of the transformer 12 issubstantially equal to the input voltage V_(S) between the instant t₁and the instant t₂, so that energy is stored in the primary winding ofthe transformer 12. At the instant t₂ the base voltage V_(b) becomessubstantially equal to 0 volts, so that the switching transistor 18 isabruptly switched off. Consequently, the stored energy is transferred tothe secondary winding 30 and ultimately, via the rectifier diode 32, toa load (not shown in the Figures) which may be connected between theoutput terminal V₀ and the second supply terminal GND. The abruptswitching off of the switching transistor 18 at the instant t₂ causes asudden increase of the collector voltage V_(C) due to the inductance ofthe primary winding. The collector voltage V_(C), therefore, issubstantially higher than the input voltage V_(S) directly after theinstant t₂. The collector voltage V_(C) subsequently starts to decreaseas is indicated by the reference numeral 44 in FIG. 2. As from a giveninstant, denoted by the reference numeral 82, the collector voltageV_(C) starts to exhibit oscillating. It is to be noted that the FIGS. 2and 3 are shown in the cited United States patent specification in thecontext of an elucidation of conventional converters. However, the FIGS.2 and 3 are also used to elucidate the known converter as described inthe cited United States patent specification. For example, the citedUnited States patent specification states that, as is shown in the FIGS.2 and 3, many conventional converters operate with a fixed switchingfrequency f. The switching frequency f is sufficiently low so that atthe instant t₃, corresponding to the instant t₁, the collector voltageV_(C) exhibits no or hardly any ringing; consequently, at the instant t₃the switching transistor 18 can be switched on again without the risk ofthe collector voltage V_(C) being much higher than the input voltageV_(S) so that the dissipation of the switching transistor 18 would beunnecessarily high. The switching transistor 18 might even becomedefective. Moreover, at the instant at which oscillating of thecollector voltage V_(C) stops it can be established with certainty thatthe transfer of energy from the transformer 12 to the load has ended.Because such conventional converters operate with a fixed switchingfrequency f which is so low that it is absolutely certain that at theinstant t₃ oscillating of the collector voltage V_(C) has vanished, suchconventional converters are not suitable for applications requiring ahigh switching frequency f. Therefore, in the known converter as shownin the cited United States patent specification steps are taken toensure that this converter is suitable for a high switching frequency f.This means mainly that the converter adapts the switching frequency feach time, that is, also when the frequency of the ringing changes, insuch a manner that the switching on of the switching transistor T₁₈takes place in response to the first minimum (in the first valley) ofthe oscillating collector voltage V_(C), said first minimum beingdenoted by the reference numeral 84 in FIG. 2. The transfer of energyfrom the transformer 12 to the load has not yet been completed at thatinstant. However, considering the fact that oscillating actually arisesonly at the instant at which the rectifier diode 32 starts to leave theconductive state, it will be evident that the major part of the energyhas already been transferred to the load. The frequency of oscillatingof the collector voltage V_(C) is dependent, for example, on the type oftransformer used. For this reason it is described in the cited UnitedStates patent that the switching frequency f of the converter should bevariable and that it should be adapted automatically so as to ensurethat the instant t₃, as indicated in FIG. 2, more or less coincides withthe first minimum 84 of the oscillating collector voltage It is adrawback of a converter in conformity with the cited United Statespatent that the switching frequency can in principle assume any value.For example, the switching frequency may thus be allowed to assume avery high value so that the efficiency of the converter could suffer. Asolution to this problem is described in international patentapplication PCT/EP00/04377. The switching means therein are notnecessarily switched on in response to the first local minimum. Thechoice of a different local minimum (in a different valley) in responseto which the switching means can be switched on is enabled by therecognition of the fact that the frequency of the ringing voltage ismuch higher than the frequency of the oscillator signal. Frequencyvariations of the voltage across the switching means then ultimatelyresult in variations in the selection of a local minimum, so that theswitching frequency of the converter remains practically constant and isactually determined by the frequency of the oscillator signal.

[0003] Even though the switching frequency of a converter in conformitywith the cited international patent application is reasonably constant,a (slight) frequency variation takes place nevertheless when theconverter switches over from a given local minimum to a different localminimum. Because this transition is very brief, it need not have adverseeffects in principle. However, it often occurs in practice that thenecessary switching frequency is not exactly compatible with a givenlocal minimum. As a result, the converter is liable to switch overcontinuously between two adjoining local minima. The switching frequencythen continuously toggles between two frequencies. This may cause anannoying noise (whistling), for example, from the transformer.

[0004] It is an object of the invention to provide a converter whicheliminates the described drawbacks.

[0005] To this end, the control circuit includes a frequency controlcircuit for controlling the switching frequency of the switching controlsignal in such a manner that the switching frequency varies within afrequency window which is determined by a lower limit frequency and anupper limit frequency, and in such a manner that, when the switchingfrequency becomes equal to the lower limit frequency or to the upperlimit frequency, the frequency control circuit adapts the switchingfrequency in such a manner that it again varies within a furtherfrequency window which is determined by a further lower limit frequencyand a further upper limit frequency, the information being adapted insuch a manner that, generally speaking, the switching means is switchedon only during a given valley other than said local valley of thevoltage across the switching means.

[0006] Because of the frequency window, the switching frequency cannotassume an arbitrarily low or high value. This eliminates the citeddrawback of the converter in conformity with the cited United Statespatent. If the amount of power taken up changes, the switching frequencyalso changes. When the correct converter is locked in a given localvalley (preferably exactly at the minimum) of the voltage across theswitching means, said valley has an associated power window in which thepower taken up may vary and the switching frequency of the switchingmeans remains within the frequency window. If the power taken up leavessaid power window, said information is adapted in such a manner that theconverter is locked in a different valley. Said different valley isassociated with another power window again. Because said other powerwindow partly overlaps the former power window, actually a so-calledhysteresis effect occurs between the locking from one valley to anothervalley. Periodic toggling of the switching frequency is thus avoided(unless the power consumption exhibits comparatively large periodicfluctuations). Annoying noise from the converter, such as a whistlingnoise from the transformer, is thus avoided.

[0007] In an embodiment of a converter in accordance with the inventionthe lower limit frequency of the further frequency window is equal tothe lower limit frequency of the frequency window, and that the upperlimit frequency of the further frequency window is the same as the upperlimit frequency of the frequency window. This offers the advantage thatonly one frequency window is required.

[0008] In an embodiment of a converter in accordance with the inventionthe information includes an evaluation signal for indicating when thevoltage across the switching means is lower than the input voltage, andalso a further evaluation signal for indicating when the time derivativeof the voltage across the switching means is approximately equal tozero. The evaluation signal ensures that the switching means can neverbe switched on when the voltage across the switching means is higherthan the input voltage. The further evaluation signal ensures, inconjunction with the evaluation signal, that the switching means,generally speaking, can be switched on only during the minimum value ofthe valley in which the converter is locked. It may be advantageous toissue a command for switching on the switching means already just beforethe time derivative of the voltage across the switching means becomesequal to zero. Said derivative then has a small negative value. This isbecause electronic control circuits always require a given responsetime. This response time can be anticipated by attempting to switch onthe switching means already when said derivative has a given smallnegative value. The exact value can be determined by experiments and/orsimulations. Despite the required response time, the switching means canthen be switched on exactly at an instant at which the voltage acrossthe switching means exhibits a local minimum.

[0009] In an embodiment of a converter in accordance with the inventionthe frequency control circuit includes: a first counter with anup-input, a down-input, and a data output; a second counter with a resetinput, an up-input and a data output; a digital comparator with a firstdata input which is coupled to the data output of the first counter, asecond data input which is coupled to the data output of the secondcounter, and an output for supplying the switching control signal; meanswhich are coupled so as to receive a first frequency reference signalwhich corresponds to the lower limit frequency and a second frequencyreference signal which corresponds to the upper limit frequency, themeans comparing the frequency of the switching control signal with thefirst frequency reference signal and with the second frequency referencesignal, and supplying, in response to said comparison, either a downsignal to the down-input or an up signal to the up-input of the firstcounter; and means for delivering a valley number signal of the ringingvoltage, said valley number signal being derived from the evaluationsignal and the further evaluation signal. A predominantly digitalimplementation is thus obtained for the frequency control circuit. Saidmeans which are coupled so as to receive the first and the secondfrequency reference signals may be constructed, for example, in such amanner that the first and the second frequency reference signals are ACsignals whose frequencies are related to the lower limit frequency andthe upper limit frequency, respectively, of the frequency window. Thefirst and the second frequency reference signals may also be, forexample, DC voltages which correspond to the lower limit frequency andthe upper limit frequency, respectively.

[0010] In an embodiment of a converter in accordance with the inventionthe means for delivering the valley number signal include an AND gatewhich has a first input for receiving the evaluation signal, a secondinput for receiving the further evaluation signal, and an output fordelivering the valley number signal to the up-input of the secondcounter. This is a very simple implementation for the means forproviding the valley number signal.

[0011] In an embodiment of a converter in accordance with the inventionthe frequency control circuit includes: a voltage-controlled oscillatorwhich has an input for receiving a VCO control voltage and an output forsupplying an oscillator signal; a first frequency control capacitor forsupplying the VCO control voltage; a second frequency control capacitor;adaptation means for adapting a voltage across the first frequencycontrol capacitor and the VCO control voltage by connecting the firstfrequency control capacitor and the second frequency control capacitorin parallel for approximately the period of time during which theswitching means are switched on, and by discharging the second frequencycontrol capacitor for approximately the period of time during which theswitching means are switched off, and by applying the voltage across thesecond frequency control capacitor with a value which is higher than thevalue of the VCO control voltage during a part of the period of timeduring which the switching means are switched off, said part beingdetermined by the oscillator signal. A predominantly analogimplementation is thus obtained for the frequency control circuit.

[0012] In an embodiment of a converter in accordance with the inventionthe frequency control circuit also includes limiting means for limitingthe voltage range of the VCO control voltage to a voltage window whichis determined by a lower voltage limit which corresponds to the lowerlimit frequency and an upper voltage limit which corresponds to theupper limit frequency. This is a simple method of defining the frequencywindow.

[0013] In an embodiment of a converter in accordance with the inventionthe previous embodiment of the frequency control circuit also includesan AND gate with a first input for receiving the evaluation signal, asecond input for receiving the further evaluation signal, a third inputfor receiving the oscillator signal, and an output for supplying theswitching control signal. This is a very simple realization to ensurethat the switching means can be switched on only if so permitted by theevaluation signal as well as the further evaluation signal and theoscillator signal.

[0014] The invention will be described in detail hereinafter withreference to the drawing; therein:

[0015]FIG. 1 shows an electrical circuit diagram of a known converter asproposed in U.S. Pat. No. 5,754,414;

[0016]FIGS. 2 and 3 show graphs elucidating the electrical circuitdiagram of FIG. 1;

[0017]FIG. 4 shows a set of diagrams I-III with a relation between theswitching frequency f of the switching control signal and the power Ptaken up in known converters (I) and the converter in accordance withthe invention (II and III) so as to provide a further explanation of theoperation of the converter in accordance with the invention;

[0018]FIGS. 5, 7, 8 and 10 show electrical circuit diagrams ofembodiments of a converter in accordance with the invention, and

[0019]FIGS. 6 and 9 show signal diagrams for a further elucidation ofthe embodiments shown.

[0020] Corresponding parts or elements are denoted by correspondingreference numerals in the FIGS. 4 to 10.

[0021] The diagram I of FIG. 4 illustrates the relationship between theswitching frequency f of the switching control signal and the power Ptaken up in the known converter in conformity with the internationalpatent application PCT/EP00/04377. The value of the switching frequencyf remains roughly constant and is represented by as the frequencyf^(OSC). If the power P taken up changes, another valley is selected;for example, switching over takes place from the valley VL₂ to thevalley VL₃. However, assume that the value of the power P taken upcorresponds to the indicated value P₀. In the known converter inconformity with the cited U.S. Pat. No. 5,754,414 the value of theswitching frequency f would become equal to the indicated (very high)value f_(VL1). In the known converter in conformity with theinternational patent application PCT/EP00/04377 no such increase takesplace, because this converter more or less dictates that the switchingfrequency f should remain (approximately) equal to the value f_(OSC).What happens is that the converter starts to toggle continuously (seethe indicated crosses) between the valley VL₂ and the valley VL₃.

[0022] The diagrams II and III of FIG. 4 show the relationship betweenthe switching frequency f of the switching control signal and the powerP taken up in the converter in accordance with the invention. In thediagram II it is indicated that the converter is locked in the thirdvalley VL₃. The value of the switching frequency f corresponds to theindicated value f₀. When the power P taken up changes, the switchingfrequency f also changes. The converter then remains locked in the thirdvalley VL₃ for as long as the switching frequency f has a value which ishigher than a lower limit frequency F_(L) and lower than an upper limitfrequency F_(H).

[0023] The diagram III of FIG. 4 shows the operation of the converteralso in the case where the lower limit frequency F_(L) or the upperlimit frequency F_(H) is reached. Assume that the power P taken upequals P₀ at a given instant, the switching frequency f being equal tof₀ and the converter being locked in the third valley VL₃. If the powerP taken up increases, the switching frequency f then decreases. When thepower P has become equal to P₂, the switching frequency f equals thelower limit frequency F_(L). The converter then switches over from thethird valley VL₃ to the second valley VL₂. This transition is indicatedby the arrow AR₁. The switching frequency f is then increased to thevalue f₂. For as long as the switching frequency f remains within thefrequency window (determined by the lower limit frequency F_(L) and theupper limit frequency F_(H)), the converter will remain locked in thesecond valley VL₂. With each valley there is associated a power windowwhich corresponds to the frequency window. For example, with the secondvalley there is associated a power window which is defined by the powersP₁ and P₄. This means that as from the instant at which the converter islocked in the second valley VL₂, it remains locked therein for as longas the power taken up is greater than P₁ and smaller than P₄. Thus, anoverlap exists between the adjoining power windows. This gives rise to ahysteresis effect so that the toggling between two adjoining valleys isavoided. It is to be noted that only one frequency window is indicatedin the diagrams II and III, and also in the embodiments of a converterin accordance with the invention which are yet to be described. However,it is in principle also possible to operate with different frequencywindows; in that case, for example, each power window corresponds to arespective frequency window.

[0024]FIG. 5 shows an electrical circuit diagram of an embodiment of aconverter in accordance with the invention. The converter includesswitching means S₀, or a switch S₀, which is alternately switched on andoff under the control of a switching control signal V_(cntrl), and aninductive element T which in the present embodiment is constructed so asto have a transformer T with a primary winding L_(P) and a secondarywinding L_(S). The switch S₀ and the primary winding L_(P) togetherconstitute a series circuit which is connected, by way of a firstconnection point, to a first supply terminal 1 and to a second supplyterminal 2, by way of a second connection point, in order to receive aninput voltage V_(in) which is supplied by a voltage source VSRC. A firstcapacitor C_(p1) is a parasitic capacitance of the primary windingL_(P). A second capacitor C_(p2) is a parasitic capacitance of theswitch S₀. A rectifier diode D₁ is coupled between a first connectionpoint of the secondary winding L_(S) and a first output terminal 3. Asecond connection point of the secondary winding L_(S) is connected to asecond output terminal 4. A smoothing capacitor C is coupled between thefirst output terminal 3 and the second output terminal 4. A load Z_(L)is coupled between the first output terminal 3 and the second outputterminal 4 in order to receive an output voltage U₀. The converter alsoincludes a control circuit C_(NTRL) for delivering a switching controlsignal V_(cntrl) to the switch S₀, and also evaluation means EVMNS forevaluating a voltage U_(S) across the switch S₀. The evaluation meansEVMNS supply the control circuit CNTRL with an evaluation signalEV_(sgnl) and with a further evaluation signal EV_(fsgnl). The controlcircuit CNTRL also includes a frequency control circuit FC forcontrolling the switching frequency f of the switching control signalV_(cntrl) in a manner such that the switching frequency f can varywithin a frequency window which is determined by the lower limitfrequency F_(L) and the upper limit frequency F_(H).

[0025] The operation of the embodiment as shown in FIG. 5 will bedescribed in detail hereinafter with reference to the set of signaldiagrams I, II, III and V as shown in FIG. 6. FIG. 6 shows the situationin which the converter is locked in the third valley VL₃ (see also FIG.4). Between the instant to and the instant t₁ the switching controlsignal V_(cntrl) has a high value such that the switch S₀ is closed.Consequently, the voltage across the primary winding L_(P) issubstantially equal to the input voltage V_(in). Between the instant toand the instant t₁ energy is stored in the primary winding L_(P) of thetransformer T. At the instant t₁ the switching control signal V_(cntrl)becomes substantially equal to zero volts, so that the switch S₀ isopened. As from the instant t₁ the energy stored in the primary windingL_(P) is transferred to the secondary winding L_(S) after which it isdelivered, via the rectifier diode D₁, to the load Z_(L). As fromapproximately an instant t_(D) the current flowing through the rectifierD₁ becomes so small that the rectifier diode D₁ acts practically as anopen connection. Consequently, as from approximately the instant t_(D)the transformer T is practically not loaded, so that a resonant circuitwhich is formed by the primary winding L_(P) and the parallel connection(via the voltage source VSCR) of the first capacitor C_(p1) and thesecond capacitor C_(p2), is practically not damped. Consequently, thevoltage U_(S) across the switch S₀ starts to oscillate. At the instantt₅ the switch S₀ is closed again, so that energy is stored once more inthe primary winding L_(P) of the transformer T.

[0026] Should the frequency of oscillating voltage U_(S) change for somereason, the switching frequency f of the switching control signalV_(cntrl) also changes so that the converter remains locked in the thirdvalley VL₃, that is, at least for as long as the switching frequency fremains within the frequency window which is defined by the lower limitfrequency F_(L) and the upper limit frequency F_(H).

[0027]FIG. 7 shows an electrical circuit diagram of an embodiment of thefrequency control circuit FC. The frequency control circuit FC includes:a first counter CNT₁ with an up-input U₁ a down-input D, and a dataoutput; a second counter CNT₂ with a reset input R, an up-input U₂ and adata output; a digital comparator DCMP with a first data input which iscoupled to the data output of the first counter CNT₁ and a second datainput which is coupled to the data output of the second counter CNT₂,and an output for supplying the switching control signal V_(cntrl);means CNV which are coupled so as to receive a first frequency referencesignal RF_(L) which corresponds to the lower limit frequency F_(L) and asecond frequency reference signal RF_(H) which corresponds to the upperlimit frequency F_(H); means for supplying a valley number signal N_(v)of oscillating voltage U_(S); and an AND gate AND₁, an output of whichis connected to the up-input U₂ and a first input of which is coupled soas to receive the evaluation signal EV_(sgnl) whereas a second input iscoupled so as to receive the further evaluation signal EV_(fsgnl). Thereset input R of the second counter CNT₂ is connected to the output ofthe digital comparator DCMP.

[0028] The operation of the embodiment of the frequency control circuitFC as shown in FIG. 7 will be described in detail hereinafter withreference to the set of signal diagrams I, II, III, IV and V as shown inFIG. 6. The AND gate AND₁ supplies the valley number signal N_(v). As isshown in FIG. 6, the valley number signal N_(v) is logic high betweenthe instants t₁ and t₅ only if the voltage U_(S) exhibits a localminimum. The fact that the valley number signal N_(v) is also logic highbetween the instants t₀ and t₁ does not disturb the operation of thesecond counter CNT₂, because this counter is then reset since theswitching control signal V_(cntrl) is logic high during the periodbetween the instants t₀ and t₁. For example, the means CNV may beconstructed in such a manner that the first and the second frequencyreference signals RF_(L) and RF_(H) are AC signals whose frequenciescorrespond to the lower limit frequency F_(L) and the upper limitfrequency F_(H), respectively, of the frequency window (see also FIG.4). For example, the first and the second frequency reference signalsRF_(L) and RF_(H) may be DC voltages which correspond to the lower limitfrequency F_(L) and the upper limit frequency F_(H), respectively. Inboth cases coupling is necessary between the output of the digitalcomparator DCMP (or a junction which represents the same information asthe switching control signal V_(cntrl)) and the means CNV.

[0029] In the case where the first and the second frequency referencesignals RF_(L) and RF_(H) are DC voltages, the means CNV may be provided(as shown in FIG. 7) with a first timer TM₁ for receiving the first DCvoltage RF_(L) and with a second timer TM₂ for receiving the second DCvoltage RF_(H).

[0030] The operation of the frequency control circuit FC as shown inFIG. 7 is as follows. In the first counter CNT₁ there is stored a valuewhich corresponds to the valley whereto the converter is locked.Therefore, if the converter is locked, for example, to the third valleyVL₃ as in the instantaneous situation of FIG. 6, the number 3 is storedin the first counter CNT₁. The second counter CNT₂ then counts thenumber of valleys after the switching off of the switch S₀ or after theswitching control signal V_(cntrl) has become logic low. This is thecase as from the instant t₁ in FIG. 6. Each time when the valley numbersignal N_(v) becomes logic high (see diagram IV of FIG. 6) the value inthe second counter CNT₂ is incremented by one. This continues until thevalue in the second counter CNT₂ becomes equal to the value in the firstcounter CNT₁. When the value in the second counter CNT₂ becomes equal tothe value in the first counter CNT₁, correspondence is detected by thedigital comparator DCMP which, in response to such detection, changesthe switching control signal V_(cntrl) from a logic low level to a logichigh level. This takes place at the instant t₅ in FIG. 6. The first andsecond timers TM₁ and TM₂ actually measure the period duration T of theswitching control signal V_(cntrl) and hence indirectly also theswitching frequency f (f=1/T). Depending on the value of this periodduration and the DC voltage levels of the first and the second frequencyreference signals RF_(L) and RF_(H), if at a given instant the periodduration of the switching control signal V_(cntrl) has become too longor too short, either the first timer TM₁ applies an up signal u to theup-input U₁ with the result that the value stored in the first counterCNT₁ is incremented by one, or the second timer TM₂ applies a downsignal d to the down-input D, with the result that the value stored inthe first counter CNT₁ is decremented by one. Assume that in the presentexample the second timer TM₂ applies a down signal d to the down-inputD; in that case the newly stored instantaneous value in the firstcounter CNT₁ becomes equal to 2. The converter is then switched overfrom the third valley VL₃ to the second valley VL₂. The second counterCNT₂ then continues to count until it reaches the value 2, because asfrom this value the digital comparator DCMP will detect that the storedvalue has become equal to the (new) stored value of the first counterCNT₁. The converter thus remains locked in the second valley VL₂ until adown-signal d or an up signal U₁ is applied again to the first counterCNT₁. The switching frequency f thus always remains within the desiredfrequency window. This is because the DC voltages RF_(L) and RF_(H)correspond to the lower limit frequency F_(L) and the upper limitfrequency F_(H), respectively.

[0031]FIG. 8 shows an electrical circuit diagram of a further embodimentof the frequency control circuit FC. The frequency control circuit FCincludes: a voltage-controlled oscillator VCO with an input VCO_(I) forreceiving a VCO control voltage V_(vco), and an output VCO_(I) forsupplying an oscillator signal OSC; a first frequency control capacitorC_(vco) for supplying the VCO control voltage V_(vco); a secondfrequency control capacitor C_(adj); adaptation means for adapting avoltage V_(adj) across the second frequency control capacitor C_(adj)and the VCO control voltage V_(vco). The adaptation means include abuffer BF; voltage supply means or a voltage source V; a first switchS₁; a second switch S₂; a third switch S₃; a current source J; and aninverter IV. The frequency control circuit FC also includes limitingmeans LMT for limiting the voltage range of the VCO control voltageV_(vco). The frequency control circuit FC also includes an AND gate AND₂with a first input for receiving the evaluation signal EV_(sgnl), asecond input for receiving the further evaluation signal EV_(fsgnl), athird input which is connected to the output VCO_(I) of the oscillatorVCO, and an output for delivering the switching control signalV_(cntrl).

[0032] The capacitor C_(vco) is connected between the input VCO_(I) anda ground reference terminal. The capacitor C_(adj) is connected, by wayof a first connection point, to the ground reference terminal and, byway of a second connection point and the switch S₃, to the inputVCO_(I). A control electrode of the switch S₂ is connected to the inputof the inverter IV and to the output of the AND gate AND₂. The firstswitch S₁ is connected, by way of a first connection point, to an outputof the buffer BF and, by way of the second connection point, to thesecond connection point of the capacitor C_(adj). A control electrode ofthe switch S₁ is connected to the output VCO_(O). The second switch S₂is connected, by way of a first connection point, to the secondconnection point of the capacitor C_(adj) and, by way of a secondconnection point, to the current source J. A control electrode of theswitch S₃ is connected to an output of the inverter IV.

[0033] The limiting means LMT include: a comparator CMP₁ with a plusinput, a minus input, and an output; a first voltage reference means, ora first voltage reference source VRF_(L); a second voltage referencemeans, or a second voltage reference source VRF_(H); a latch LTCH with aset input, a reset input, and a q output; a fourth switch S₄; and adiode D₂. The voltage reference source VRF_(L) is connected between theplus input of the comparator CMP₁ and the ground reference terminal. Theminus input of the comparator CMP₁ is connected to the input VCO_(I).The output of the comparator CMP₁ is connected to the set input of thelatch LTCH. The reset input of the latch LTCH is connected to the outputVCO_(O). The voltage reference source VRF_(H) is connected between afirst connection point of the switch S₄ and the ground referenceterminal. A second connection point of the switch S₄ is connected to theinput VCO_(I). A control electrode of the fourth switch S₄ is connectedto the q output of the latch LTCH. The diode D₂ is coupled parallel tothe switch S₄.

[0034] The operation of the frequency control circuit FC as shown inFIG. 8 will now be described in detail with reference to the set ofsignal diagrams I, II, III, V, VI and VII of FIG. 9. A voltage V_(vco)(see the dashed signal line in the diagram VII of FIG. 9) across thecapacitor C_(vco) determines the frequency of the oscillator signal OSCand hence the switching frequency f of the switching control signalV_(cntrl). The diagram VII of FIG. 9 also shows, in the form of anon-interrupted signal line, a voltage V_(adj) across the capacitorC_(adj). The oscillator signal OSC is represented in the diagram VI ofFIG. 9. In the present example the oscillator signal OSC changes from alogic low value to a logic high value at the instant t_(A) and from alogic high value to a logic low value at the instant t_(B). At theinstant to the switch S₀ (see FIG. 5) is switched on because theswitching control signal V_(cntrl) assumes a logic high value. Theswitching control signal V_(cntrl) remains logic high between theinstant to and the instant t₁. The switch S₃ is switched on and theswitch S₂ is switched off between the instant to and the instant t₁. Theswitch S₁ is switched off between the instant to and the instant t_(A)because the oscillator signal OSC then has a logic low value. At theinstant to the capacitors C_(adj) and C_(vco) are actually coupled inparallel. Consequently, the voltages V_(adj) and V_(vco) become equalwithin a comparatively short period of time. (Because in the presentexample the voltage V_(vco) was higher than the voltage V_(adj) prior tothe instant t₀, the voltage V_(adj) increases directly after the instantt₀ while the voltage V_(vco) decreases). The voltages V_(adj) andV_(vco) remain equal until the instant t₁ at which the switching controlsignal V_(cntrl) assumes a logic low value again and hence the switch S₀is switched off again. Because the switch S₃ is switched off again asfrom the instant t₁ and because the voltage V_(vco) is still (roughly)below the voltage value VRF_(H) and hence the limiting means LMT do notform a load for the capacitor C_(vco), the voltage V_(vco) remainsconstant as from the instant t₁. However, the voltage V_(adj) decreasesbetween the instant t₁ and the instant t_(A), because the switch S₂ isswitched on so that the capacitor C_(adj) is discharged via the currentsource J. The fact that the voltage V_(adj) linearly decreases betweenthe instant t₁ and the instant t_(A) in the diagram VII of FIG. 9 is dueto the fact that the current source J delivers a constant current. Thisis not strictly necessary. The current source J, for example, may bereplaced by a resistor so that the current decrease between the instantt₁ and the instant t_(A) is not linear.

[0035] At the instant t_(A) the oscillator signal OSC becomes logichigh, so that the switch S₁ is switched on. The buffer BF, having a lowoutput impedance, thus enforces a voltage on the capacitor C_(adj).Because an input of the buffer BF is connected, via the voltage source Vwhich supplies a voltage having a value V, to the input VCO_(i), at theinstant t_(A) the voltage becomes equal to the voltage V_(vco) increasedby the voltage V. This remains so until at the instant t_(B) theoscillator signal OSC becomes logic low again. Because the switchingcontrol signal V_(cntrl) still has a logic low value between the instantt_(B) and the instant t₅, and hence the switch S₂ is still switched on,the capacitor C_(adj) is discharged again by the current source J.

[0036] If at the instant t₅ the voltages V_(vco) and V_(adj) are exactlyequal, as in the example illustrated in FIG. 9 (diagram VII), theoscillator frequency is no longer changed (for as long as no changesoccur in, for example, the load) and the converter remains locked in therelevant valley (being the valley VL₃ in FIG. 9). However, if changesoccur, the oscillator VCO will adapt its frequency again, and hence alsothe switching frequency f. However, if the frequency drops below thelower limit frequency F_(L) or rises beyond the upper limit frequencyF_(H) (see FIG. 4), the converter has to switch over to a differentvalley. Because the voltage V_(vco) determines the frequency of theoscillator signal VCO, therefore, a relationship exists between avoltage window concerning the voltage V_(vco) and the frequency window.The frequency window is defined by a lower value of the voltage V_(vco)which corresponds to the lower limit frequency F_(L) and by an uppervalue of the voltage V_(vco) which corresponds to the upper limitfrequency F_(H). These voltage limits of the voltage V_(vco) are imposedby means of the voltage reference source VRF_(L) and the voltagereference source VRF_(H) (the threshold voltage of the diode D₂ isignored in this context).

[0037] When the voltage V_(vco) becomes higher than the voltage VRF_(H),and hence the upper limit frequency F_(H) is reached, the diode D₂becomes conductive so that the voltage V_(vco) cannot increase further.Consequently, the converter automatically switches over to a differentvalley, for example, from the third valley VL₃ to a fourth valley VL₄,so that the switching frequency f becomes lower again and hence thevoltage V_(vco) will ultimately become lower again than V_(RFH).Analogously, when the voltage becomes lower than the voltage VRF_(L) thevoltage V_(vco) can be limited so that the converter automaticallyswitches over to a different valley, for example, from the third valleyVL₃ to the second valley VL₂. In this context, however, the frequencycontrol circuit FC as shown in FIG. 8 also has a special and also simpleembodiment. As soon as the voltage V_(vco) becomes lower than thevoltage VRF_(L), and hence the lower limit frequency F_(L) is reached,the voltage at the output of the comparator CMP₁ changes from a logiclow value to a logic high value. As a result, the voltage at the qoutput of the latch LTCH becomes logic high, so that the switch S₄ isswitched on. The input VCO₁ is thus short-circuited to the voltagereference source VRF_(H). Consequently, the voltage V_(vco) is thusincreased from the lower limit value VRF_(L) to the upper limit valueVRF_(H) within a very brief period of time, so that actually at thatinstant briefly the above situation occurs in which the voltage V_(vco)can no longer increase and the converter automatically switches over toa different valley. The switch S₄ remains switched on until theoscillator signal OSC again switches over from a logic low value to alogic high value. This is because the signal on the reset input of thelatch LTCH then becomes logic high, so that the q output becomes logiclow again.

[0038]FIG. 10 shows an electrical circuit diagram of an embodiment of aconverter in accordance with the invention. The converter includes acomparator CMP₂ which is coupled, by way of an output, to the frequencycontrol circuit FC of the control circuit CNTRL in order to supply theevaluation signal EV_(sgnl). The comparator CMP₂ has a plus input whichis connected to the first supply terminal 1 and a minus input which isconnected to the common junction of the primary winding L_(P) and theswitch S₀. Consequently, the evaluation signal EV_(sgnl) is at a highlevel only when the voltage U_(S) is lower than the input voltageV_(in). (See also the signal diagrams I and III of the FIGS. 6 and 9.)The converter also includes a differentiator DF which is connected, byway of an input, to the common junction of the primary winding L_(P) andthe switch S₀ and is coupled, by way of an output, to the frequencycontrol circuit FC of the control circuit CNTRL in order to deliver thefurther evaluation signal EV_(fsgnl). The further evaluation signalEV_(fsgnl) is at a high level only if the time derivative of the voltageUs is approximately equal to zero. (See also the signal diagrams I andII of the FIGS. 6 and 9.)

[0039] The differentiator DF includes a first bipolar transistor Q₁whose collector and base are interconnected and whose emitter isconnected to the second supply terminal 2; a second bipolar transistorQ₂ whose emitter is connected to the second supply terminal 2 and whosebase is connected to the base of the first bipolar transistor Q₁ whileits collector forms the output of the differentiator DF; a third bipolartransistor Q₃ whose emitter is connected to the collector of the firstbipolar transistor Q₁ while its collector is connected to the collectorof the second bipolar transistor Q₂; a capacitor CDF which is coupledbetween the common junction of the primary winding L_(P) and the switchS₀ and the emitter of the third bipolar transistor Q₃; a referencevoltage source V_(RF) which is coupled between a base of the thirdbipolar transistor Q₃ and the second supply terminal 2; and a referencecurrent source IRF which is coupled to the output of the differentiatorDF.

[0040] The operation of the differentiator DF is as follows. The firstand the second bipolar transistor Q₁ and Q₂ together constitute acurrent mirror. A positive current (that is a current in the directionof the emitter and the collector of the third and the first bipolartransistor Q₃ and Q₁, respectively) through the capacitor C_(DF) ismirrored by the current mirror and hence appears in inverted form at theoutput of the current mirror, which output is formed by the collector ofthe second bipolar transistor Q₂. A negative current through thecapacitor C_(DF) flows through the third bipolar transistor Q₃ (and notthrough the current mirror) and hence is not inverted. Thedifferentiator DF, as shown in FIG. 10, actually operates as a currentrectifier. When the absolute value of the positive or the negativecurrent through the capacitor C_(DF) is (approximately) smaller than thecurrent delivered by the reference current source I_(RF), the furtherevaluation signal EV_(fsgnl) has a high level while otherwise the levelof the further evaluation signal EV_(fsgnl) is low.

[0041] The further evaluation signal EV_(fsgnl) is also influenced bythe current mirror ratio of the current mirror. This effect enables acommand for switching on the switch S₀ to be issued already just beforethe time derivative of the voltage U_(S) across the switch S₀ equalszero (and hence has a slight negative value) in order to compensate theinevitable response time of electronic control circuits. The currentmirror ratio of the current mirror can be adapted, for example, byadaptation of the ratio of emitter surfaces of the first bipolartransistor and the second bipolar transistor Q₁ and Q₂.

[0042] The differentiator DF may also be implemented completely orpartly while utilizing field effect transistors.

[0043] The converter may also be equipped with other types ofdifferentiator. It is alternatively possible to use a single coilinstead of the transformer T. The switch S₀ may be constructed, forexample, by means of a MOS transistor, a bipolar transistor, a thyristoror a relay. The converter can be realized as an integrated circuit aswell as by means of discrete components.

1. A converter for converting an input voltage between a first supplyterminal and a second supply terminal to an output voltage, whichconverter includes switching means which, in the operating state, arealternately switched on and off under control of a switching controlsignal, an inductive element which forms a series circuit in conjunctionwith the switching means, which series circuit is coupled between thefirst supply terminal and the second supply terminal, a control circuitfor supplying the switching control signal, and evaluation means forevaluating a voltage across the switching means, said voltage exhibitingoscillating, and for supplying the control circuit with information soas to ensure that, generally speaking, the switching means are switchedon only during a given local valley of the voltage, the control circuitincluding a frequency control circuit for controlling the switchingfrequency of the switching control signal in such a manner that theswitching frequency varies within a frequency window which is determinedby a lower limit frequency and an upper limit frequency and in such amanner that, when the switching frequency becomes equal to the lowerlimit frequency or to the upper limit frequency, the frequency controlcircuit adapts the switching frequency in such a manner that it againvaries within a further frequency window which is determined by afurther lower limit frequency and a further upper limit frequency, theinformation being adapted in such a manner that, generally speaking, theswitching means is switched on only during a given valley other thansaid valley of the voltage across the switching means.
 2. A converter asclaimed in claim 1, wherein the lower limit frequency of the furtherfrequency window is equal to the lower limit frequency of the frequencywindow, and that the upper limit frequency of the further frequencywindow is equal to the upper limit frequency of the frequency window. 3.A converter as claimed in claim 1, wherein the information includes anevaluation signal for indicating when the voltage across the switchingmeans is lower than the input voltage, and also a further evaluationsignal for indicating when the time derivative of the voltage across theswitching means is approximately equal to zero.
 4. A converter asclaimed in claim 2, wherein the frequency control circuit includes: afirst counter with an up-input, a down-input, and a data output; asecond counter with a reset input, an up-input and a data output; adigital comparator with a first data input which is coupled to the dataoutput of the first counter, a second data input which is coupled to thedata output of the second counter, and an output for supplying theswitching control signal; means which are coupled so as to receive afirst frequency reference signal which corresponds to the lower limitfrequency and a second frequency reference signal which corresponds tothe upper limit frequency, the means comparing the switching frequencyof the switching control signal with the first frequency referencesignal and with the second frequency reference signal and supplying, inresponse to said comparison, either a down signal to the down-input oran up signal to the up-input of the first counter; and means fordelivering a valley number signal of the ringing voltage, said valleynumber signal being derived from the evaluation signal and the furtherevaluation signal.
 5. A converter as claimed in claim 4, wherein themeans for delivering the valley number signal include an AND gate whichhas a first input for receiving the evaluation signal, a second inputfor receiving the further evaluation signal, and an output fordelivering the valley number signal to the up-input of the secondcounter.
 6. A converter as claimed in claim 2, wherein the frequencycontrol circuit includes: a voltage-controlled oscillator which has aninput for receiving a VCO control voltage, and an output for supplyingan oscillator signal; a first frequency control capacitor for supplyingthe VCO voltage; a second frequency control capacitor; adaptation meansfor adapting a voltage across the first frequency control capacitor andthe VCO control voltage by connecting the first frequency controlcapacitor and the second frequency control capacitor in parallel forapproximately the period of time during which the switching means areswitched on, and by discharging the second frequency control capacitorfor approximately the period of time during which the switching meansare switched off, and by applying the voltage across the secondfrequency control capacitor with a value which is higher than the valueof the VCO control voltage during a part of the period of time duringwhich the switching means are switched off, said part being determinedby the oscillator signal.
 7. A converter as claimed in claim 6, whereinthe frequency control circuit also includes limiting means for limitingthe voltage range of the VCO control voltage to a voltage window whichis determined by a lower voltage limit which corresponds to the lowerlimit frequency and an upper voltage limit which corresponds to theupper limit frequency.
 8. A converter as claimed in claim 7, wherein thefrequency control circuit also includes an AND gate with a first inputfor receiving the evaluation signal, a second input for receiving thefurther evaluation signal, a third input for receiving the oscillatorsignal, and an output for supplying the switching control signal.